Wireless and mobile devices depend upon various key requirements, such as minimizing power usage. Power consumption carries the heavy burden of impacting battery life on these portable devices such as cellular phones and PDAs. Maximizing the amount of battery life is very important while being able to maintain performance and minimize cost. Memories consume power even when in a standby mode and are not actively contributing anything to the operation of these portable devices. Also, the percentage of memory elements on a chip is rising. The combination of these two trends suggest that leakage reduction may be required in memory elements when the overall power consumption of the chip is a concern.
Power dissipation in embedded SRAMs fall into two main categories: active power dissipation and standby power dissipation. Active power is described as power consumed during the standard operation of the memory and is typically measured in milliwatts per megahertz (mW/MHz). Standby power dissipation for most CMOS circuits can be due to leakage currents. Assuming the bit lines are precharged to high voltage, these devices have subthreshold leakage from drain to source.
During standby operations bit lines and source lines may be held at the same potential, such as both being in a high voltage state. During an active read operation on a given bit cell, the corresponding source line is, for example, pulled low and word line is turned on. If the particular bit cell being read is programmed as a zero then the bit line discharges through the bit cell's transistor. If the bit cell is programmed as a one, then the bit line should remain high.
Yet, two phenomena may prevent the bit line of a bit cell programmed as a one from staying at a high voltage state during the read operation. Other bit cells that are programmed as zero's and share the same bit line and source line may have sub-threshold leakage current through their existing transistors. The cumulative effect of enough leakage current from these bit cells sharing the same bit line may cause the voltage level of that bit line to decrease to a point where it should be recharged. Also, source line to bit line coupling can cause an adjacent bit line to drop in voltage level.
Some prior art memory arrays can only place an entire memory array rather then portions of the memory array in standby to reduce power consumption. These memories may send a chip select (CS) signal to isolate the entire memory array from a VCC power potential. Also, these memory arrays are not self-biasing to control a floating voltage potential in the isolated memory array because the gate of the limiting component does not sense the magnitude of the floating voltage. Some other prior art memory arrays add additional bias circuits to control the voltage potential of floating voltage potential in the isolated memory array. However, these memory arrays are also not self-biased to control a floating voltage potential in the isolated memory array because the gate of the limiting component does not sense the magnitude of the floating voltage. Rather the limiting component senses the voltage of the biasing circuit. Appropriate regulation of the floating voltage potential can be important. If the floating voltage coupled to a memory cell rises too high, the integrity of the contents stored in the memory cell may be compromised. Use of additional bias circuits may not be desirable because the additional circuits increase the total power consumption of the memory.